1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device that includes plural SRAM cells.
2. Description of Related Art
An SRAM (Static Random Access Memory) is used as a semiconductor memory device. The SRAM can be formed in a standard semiconductor CMOS process, and is widely used in a system LSI and the like. A memory cell of the SRAM includes an N-well region, a drive transistor formed on a P-well region, a load transistor, and a transfer transistor. In this case, it is necessary to supply a well potential to each of the N-well region and the P-well region.
Techniques disclosed in Patent Documents 1 and 2 discloses a semiconductor memory device where a well potential supply region used to supply a well potential is provided in each unit SRAM cell.
Meanwhile, Patent Document 3 discloses a semiconductor memory device including plural unit SRAM cells, each of which includes eight transistors. FIG. 1 is a circuit diagram showing an SRAM cell 100 disclosed in Patent Document 3.
The SRAM cell 100 includes NMOS drive transistors N13 and N31, load transistors P11 and P21, first transfer transistors N11 and N22, second NMOS transfer transistors N12 and N21, word lines WLX and WLY, and bit lines BIT and /BIT. The drive transistor N13 and the load transistor P11 are connected in series between a power source potential VDD and a ground potential VSS. Further, the drive transistor N31 and the load transistor P21 are connected in series between the power source potential VDD and the ground potential. Furthermore, the first and second transfer transistors N11 and N12, which are connected in series, are connected between the bit line BIT and a node ND that is formed between the drive transistor N13 and the load transistor P11. The first and second transfer transistors N22 and N21, which are connected in series, are connected between the bit line /BIT and a node /ND that is formed between the drive transistor N31 and the load transistor P21. Further, gates of the first transfer transistors N11 and N22 are connected to the word line WLY, and gates of the second transfer transistors N12 and N21 are connected to the word line WLX.
FIG. 5 is a view showing the layout of a semiconductor memory device including SRAM cells 100 shown in FIG. 1. Meanwhile, the semiconductor memory device shown in FIG. 5 has a layout where plural SRAM cells disclosed in Patent Document 3 is provided. Further, FIG. 6 are cross-sectional views of the SRAM cell 100 shown in FIG. 5 taken along the C-C′ and D-D′ lines, respectively. In the SRAM memory cell 100, a P-well region Pwell1, a P-well region Pwell2, and an N-well region Nwell are formed on the semiconductor substrate (P-type substrate). As shown in FIG. 5 and FIG. 6, the drive transistor N13 is formed in the P-well region Pwell1 by N-type diffusion layers DN3 and DN4 and polysilicon wiring PL1, and the drive transistor N31 is formed in the P-well region Pwell2 by N-type diffusion layers DN5 and DN6 and polysilicon wiring PL2. The load transistor P11 is formed in the N-well region Nwell by P-type diffusion layers DP1 and DP2 and the polysilicon wiring PL1, and the load transistor P21 is formed in the N-well region Nwell by P-type diffusion layers DP3 and DP4 and the polysilicon wiring PL2. Further, the first transfer transistor N11 is formed in the P-well region Pwell1 by N-type diffusion layers DN1 and DN2 and polysilicon wiring PL3, and the second transfer transistor N12 is formed in the P-well region Pwell1 by the N-type diffusion layers DN2 and DN3 and polysilicon wiring PL4. The second transfer transistor N21 is formed in the P-well region Pwell2 by N-type diffusion layers DN6 and DN7 and polysilicon wiring PL5, and the first transfer transistor N22 is formed in the P-well region Pwell2 by N-type diffusion layers DN7 and DN8 and polysilicon wiring PL6.
[Patent Document 1] Japanese Patent Laid Open Application No. 2004-200702
[Patent Document 2] Japanese Patent Laid Open Application No. 2005-236282
[Patent Document 3] Japanese Patent Laid Open Application No. 2006-210736